There have been previously known apparatus and methods for fabricating circuits at the interconnection bonding pads of metal-oxide semiconductor ("MOS") devices to prevent damage to internal circuitry caused by ESD pulses.
One such circuit is described in U.S. Pat. No. 4,692,781 of Roundtree et al. FIGS. 1 and 2 hereof show and assist in the explanation of the operation of the Roundtree et al. prior art ESD protection circuit for a MOS device. With reference to FIG. 1, a metal bonding pad 10 is electrically connected by a metal conductor 11 to a drain 12 of a field-effect transistor ("FET") 13. FET 13 has a gate 14 electrically connected to drain 12 and a source 15 electrically connected to a substrate 16. When the voltage present at pad 10 is a positive threshold voltage exceeding about +20 to +25 volts with respect to substrate 16, FET 13 enters secondary breakdown and conducts heavily to substrate 16. When the voltage present at pad 10 is negative with respect to the voltage of substrate 16, substrate 16 and drain 12 act as a forward-biased diode and conduct current from substrate 16 into pad 10. Drain 12 of FET 13 is also connected to one end of a resistor 17, formed by a resistive interconnect path. The other end of resistor 17 is connected to a drain 18 of a MOS transistor 19 that functions as a diode. A source 20 and a gate 21 of MOS transistor 19 are connected to substrate 16 at respective metal-to-silicon contacts 22 and 23. Together, resistor 17 and transistor 19 act as an isolation stage between pad 10 and the internal circuitry of the MOS device. Drain 18 is connected to the internal circuitry of the MOS device (for example an address buffer) at a metal-to-silicon contact 24.
FIG. 2 schematically illustrates the structure of FET 13 and shows a thick field oxide 26 beneath gate 14. Field oxide 26 is subject to voltage breakdown of about 50 volts and adds capacitance at metal bonding pad 10. When FET 13 heavily conducts electrical current in response to an ESD pulse, most of the current flows in a channel 28 and thereby causes excessive heating in the region between channel 28 and source 15. Excessive current flow in drain 12 can cause "contact spiking" damage between a contact 30 and a substrate 32. The highest voltage levels such protection circuits withstand is about 7 to 8 kilovolts. However, such prior art ESD protection circuits have different conduction mechanisms for protecting against positive and negative ESD pulses resulting in better protection against negative ESD pulses than positive ESD pulses. Therefore, an ESD protection circuit rated at "8 kilovolts" may actually protect against positive ESD pulses of only 1 kilovolt or less.
Most MOS devices with this degree of voltage protection are not usually damaged by routine handling, but the trend toward smaller device geometries has made some MOS devices more susceptible to damage caused by ESD voltage and current. Smaller device geometries also result in lower device capacitances to allow higher device switching speeds. Prior art ESD protection circuits have a relatively high capacitance that limits the speed capability of small geometry MOS devices.
In response to such trends, ESD protection standards have evolved that dictate an increased degree of ESD protection. ESD protection tests are currently based on two electrical models known as the "human model" and the "machine model."
The human model is described in MIL Standard 883-C as a 100 picofarad capacitor in series with a 1.5 kiloohm resistor incorporated in an ESD probe. The probe is charged to 1 kilovolt and discharged into each interconnection pad of the MOS device. During discharge, the ESD voltage at the MOS device rises to 1 kilovolt after 10 nanoseconds of discharge and falls to zero volts after 150 nanoseconds of discharge. The 1.5 kilo-ohm resistor limits peak discharge current to 0.67 amperes. To pass the human model ESD test, a MOS device must survive ESD voltage pulses of both positive and negative polarities. Positive ESD pulses cause damage in prior art protection circuits because of contact spiking and gate breakdown.
The machine model (also known as the Japan model) is a 200 picofarad capacitor incorporated in an ESD probe. The probe is charged to 200 volts and discharged into each interconnection pad of the MOS device. During discharge, the ESD voltage at the MOS device rises rapidly to 200 volts and falls to zero volts as a damped oscillation. Peak discharge current can be very high because there is no current-limiting resistor. To pass the machine model ESD test, a MOS device must survive high ESD current pulses of both positive and negative polarities. Such current pulses often cause thermal destruction of features within prior art ESD protection circuits.
Both ESD models present problems for prior art ESD protection circuits. What is needed, therefore, is a low-capacitance ESD protection circuit that is able to protect MOS devices from ESD voltage pulses of both voltage polarities and from the high discharge currents generated by the machine model probe.